Table of contents
Arithmetic Circuits
Parent: Digital Circuits
Subject: Computer Science
Type: Semester
SL#: 2403250954
Status: Current

Following are the interactive versions of the circuits used in the document:

Arithmetic circuits are used to perform several different arithmetic operations using a single composite circuit. Half adder, subtractors etc., are examples of arithmetic circuits.

Half Adder

Half adder is an arithmetic circuit that performs arithmetic addition of two binary digits. Following is the details of a half adder.

Block diagram

Block diagram of a half adder

Truth table

ABSC
0000
0110
1010
1101

Circuit diagram

Circuit diagram of a half adder

Working

  • It has two inputs AA and BB, and two outputs sum SS, and carry CC.

  • The sum is derived with XOR operation on the inputs:

    S=AB=AˉB+ABˉ\begin{align*} S&=A\oplus B\\ &=\bar{A}B+A\bar{B} \end{align*}
  • The carry is generated by AND operation on the inputs:

    C=A.B C=A.B

Full Adder

A full adder is a combinational circuit that performs arithmetic sum of three input bits, {A,B,C}\{A,B,C\} and produces a sum SS and carry CC.

Block diagram

Block diagram of a full adder

Truth table

ABCSC
00000
00110
01010
01101
10010
10101
11001
11111

Circuit diagram

Circuit diagram of a full adder

Working

  • It consists of three inputs denoted by AA (augend bit), and BB (addend bit), and third input CC, which represents the carry from the previous lower significant bit.

  • It produces two outputs sum SS, and carry CC.

  • From the above truth table using S.O.P. (sum of products), the formula of sum is derived as follows:

S=AˉBˉC+AˉBCˉ+ABˉCˉ+ABC=Aˉ(BˉC+BCˉ)+A(BˉCˉ+BC)=Aˉ(BC)+A(BC)=ABC\begin{align*} S&=\bar{A}\bar{B}C+\bar{A}B\bar{C}+A\bar{B}\bar{C}+ABC\\ &=\bar{A}(\bar{B}C+B\bar{C})+A(\bar{B}\bar{C}+BC)\\ &=\bar{A}(B\oplus C)+A(\overline{B\oplus C})\\ &=A\oplus B\oplus C \end{align*}
  • From the above truth table using S.O.P. the formula of carry is:
S=AˉBC+ABˉC+ABCˉ+ABC=AˉBC+ABˉC+AB(Cˉ+C)=AˉBC+ABˉC+AB[xˉ+x=1]=B(AˉC+A)+ABˉC=BC+A(B+BˉC)[xˉy+x=y+x]=AB+BC+AC\begin{align*} S&=\bar{A}BC+A\bar{B}C+AB\bar{C}+ABC\\ &=\bar{A}BC+A\bar{B}C+AB(\bar{C}+C)\\ &=\bar{A}BC+A\bar{B}C+AB&&[\because\bar{x}+x=1]\\ &=B(\bar{A}C+A)+A\bar{B}C\\ &=BC+A(B+\bar{B}C)&&[\because\bar{x}y+x=y+x]\\ &=AB+BC+AC \end{align*}

4-bit Parallel Adder

This circuit is capable of adding two 4-bit binary numbers resulting in four bit sum and a carry.

Construction

Binary bits:

Four binary bits in binary addition

Design:

Four binary bits adder construction

  • Two 4-bit binary numbers are in storage AA and BB.
  • Four full adders are used.
  • The CinC_{in} input is always 0.
  • AiA_i and BiB_i and carry from the significant bit is fed as input to produce sum SiS_i and the carry generated is forwarded to the next full adder.
  • CoutC_{\textnormal{out}} is the final carry

Working

  • In least significant bit, A0A_0, B0B_0, and CinC_{\textnormal{in}} (which is 0) are added to produce sum S0S_0 and carry C0C_0.
  • Similarly all the other inputs are added in respective full adders.
  • If no carry is generated 0 is forwarded.
  • In case a fifth bit is generated in the final sum it is produced through CoutC_{\textnormal{out}}.

4-bit Combined Paraller Adder/Subtractor

The 4-bit parallel adder/subtractor circuit is capable of performing both addition and subtraction on two binary numbers.

Construction

Four binary bits adder/subtractor construction

  • Two 4-bit numbers are stored in storage AA and BB.
  • AiA_i bits are fed into the full adders directly.
  • The BiB_i inputs are fed via XOR gates.
  • The other input of XOR gate are kept common and connected to the input of first full adder known as mode.

Working

When mode is 0, we can understand the working if we concentrate on the first full adder, the inputs are:

A0+(B00)+0= A0+B0[B00=B0]\begin{align*} &A_0+(B_0\oplus0)+0\\ =\ &A_0+B_0&&[\because B_0 \oplus 0 =B_0] \end{align*}

Therefore, the circuit acts as an adder circuit.

But when mode is 1, the inputs are:

A0+(B01)= A0+B0[B01=B0]= A0+(2’s compliment of B0)= A0+(B0)= A0B0\begin{align*} &A_0+(\overline{B_0}\oplus1)\\ =\ &A_0+B_0&&[\because \overline{B_0}\oplus1=\overline{B_0}]\\ =\ &A_0+(\textnormal{2's compliment of }B_0)\\ =\ &A_0+(-B_0)\\ =\ &A_0-B_0 \end{align*}

Therefore, the circuit acts as a subtractor.

Half Subtractor

A half subtractor is an arithmatic circuit used to subtract two binary digits. It takes in two inputs AA and BB, and returns two outputs: difference (DD), and borrow (B0B_0).

Block diagram

Half subtractor block diagram

Truth table

AABBCCB0B_0
0000
0111
1010
1100

Circuit diagram

Half subtractor circuit diagram

Construction

  • Two inputs AA and BB are passed directly into the XOR gate which gives the difference DD.
  • The inputs from AA is first passed into the NOT gate then along with BB is passed into the AND gate giving the borrow B0B_0.

Working

  • The formula for the difference can be brought out using the truth table:

    D=AˉB+ABˉ=AB\begin{align*} D&=\bar{A}B+A\bar{B}\\ &=A\oplus B \end{align*}

    The above is a formula of a XOR gate.

  • The formula for borrow can be brought out using truth table as:

    B0=AˉB \begin{align*} B_0=\bar{A}B \end{align*}

Full Subtractor

A full subtractor accepts three input lines of binary digits and returns their difference and respective borrows.

Block diagram

Full subtractor block diagram

Truth table

AABBCCDDB0B_0
00000
00111
01011
01101
10010
10100
11000
11111

Circuit diagram

Circuit diagram for full subtractor

Construction

  • There are three input lines, which are passed directly into the XOR gate, which gives us the difference DD.
  • And two consequetive lines from three input with each combination with a NOT gate through AA, and noral lines through others are passed into respective AND gates to form, AˉB\bar{A}B, AˉC\bar{A}C, and BCBC combinations.
  • Finally the three combinations are passed into an OR gate to get the final borrow B0B_0

Working

  • Using S.O.P., we can find the formula for difference from the truth table as:

    D=AˉBˉC+AˉBCˉ+ABˉCˉ+ABC=Aˉ(BˉC+BCˉ)+A(BˉCˉ+BC)=Aˉ(BC)+A(BC)[xˉy+xyˉ=xy and, xˉyˉ+xy=xy]=ABC[xˉy+xyˉ=xy]\begin{align*} D&=\bar{A}\bar{B}C+\bar{A}B\bar{C}+A\bar{B}\bar{C}+ABC\\ &=\bar{A}(\bar{B}C+B\bar{C})+A(\bar{B}\bar{C}+BC)\\ &=\bar{A}(B\oplus C)+A(\overline{B\oplus C})&&[\because \bar{x}y+x\bar{y}=x\oplus y\textnormal{ and, }\bar{x}\bar{y}+xy=\overline{x\oplus y}]\\ &=A\oplus B\oplus C&&[\because \bar{x}y+x\bar{y}=x\oplus y] \end{align*}

    Therefore, the result is that of a XOR gate

  • Using K-map, the formula for borrow can be brought out as:

    K-map for borrow of full subtractor

    From the blue region, we have AˉC\bar{A}C as common, from yellow region, we have AˉB\bar{A}B as common, and from the green region we have, BCBC common.

    B0=AˉB+BC+AˉC\begin{align*} B_0&=\bar{A}B+BC+\bar{A}C \end{align*}
Docs
AnanyaGB
About
© MIT - 2024