Table of contents
Combinational Circuits
Parent: Digital Circuits
Subject: Computer Science
Type: Semester
SL#: 2403280944
Status: Current

Following are the interactive versions of the circuits used in the document:

Combinational circuits are very well known components in digital electronics which can provide output instantly based on the current input. Unlike sequential circuits, a combinational circuit listens for input signal and and generates output no matter what is the past input or state as it has no feedback or memory component. It only cares about present input and state.

Multiplexer

A multiplexer is a combinational circuit that selects one digital information from several sources, and sends it on a single output line.

It is also called data selector.

Block diagram

Block diagram of a 4\times 1 MUX

Truth table

S1S_1S0S_0Output
00A
01B
10C
11D

Construction

  • It has 2n2^n input lines.
  • It has nn select lines.
  • It has only one output line.
  • E!E! or Eˉ\bar{E} stands for low input enable line.
  • Only one of the input line gets selected depending upon the select lines as shown in the truth table.

Circuit diagram

Circuit diagram of a 4\times 1 MUX

Working

When, S1=0S_1=0, and S0=0S_0=0:

  • AND gate 1 = I1.1.1=I1I_1.1.1=I_1
  • AND gate 2 = I2.1.0=0I_2.1.0=0
  • AND gate 3 = I3.0.1=0I_3.0.1=0
  • AND gate 4 = I4.0.0=0I_4.0.0=0

Finally the OR gate = I1+0+0+0=I1I_1+0+0+0=I_1. Hence input I1I_1 is selected. Similarly in other cases their respective inputs are selected.

Applications

  • Data routing
  • Logic function generator
  • Parallel to serial convertor

Demultiplexer

It is a combinational circuit that receives information on a single input line and transmits the same information over one of several (2n2^n) output lines.

It is also called data distributor.

Block diagram

Block diagram of a 1\times 4 DEMUX

Truth Table

S1S_1S0S_0Output line
00A
01B
10C
11D

Construction

  • Has single input line.
  • It has nn select lines.
  • It has 2n2^n output lines.
  • It has one active low enabled line.

Circuit diagram

Circuit diagram of a 1\times 4 DEMUX

Working

When, S1=0S_1=0, and S0=0S_0=0:

  • AND gate 1 receives I.1.1=II.1.1=I
  • AND gate 2 receives I.0.1=0I.0.1=0
  • AND gate 3 receives I.1.0=0I.1.0=0
  • AND gate 4 receives I.0.0=0I.0.0=0

Hence, D0D_0 line is selected. Similarly the other lines are selected for their respective combinations of S1S_1 and S0S_0.

Applications

  • Serial to parallel convertor
  • Seperates signals from mixed signals
  • Used in communication system

Decoder

A decoder is a logic circuit that converts nn-bit binary inputs into 2n2^n output lines, such that each output line will be activated for only one of the possible combination of inputs.

Block diagram

Block diagram of a 2\times 4 decoder

Truth table

AABBD1D_1D2D_2D3D_3D4D_4
001000
010100
100010
110001

Circuit diagram

Circuit diagram of a 2\times 4 decoder

Working

When, A=0A=0, and B=0B=0:

  • AND gate 1 receives 1.1=11.1=1
  • AND gate 2 receives 1.0=01.0=0
  • AND gate 3 receives 0.1=00.1=0
  • AND gate 4 receives 0.0=00.0=0

Thus, the D0D_0 line gets activated and the rest are all deactivated. Similarly all other lines get active for their respective combination of inputs.

Application

  • Data demultiplexing
  • Digital display
  • Digital to analogue convertor
  • Memory adressing

Encoder

An encoder is a combinational logic circuit that converts an active input signal into a coded output signal. It encodes one of the nn active input to a coded binary output with nn-bits.

nmf(n)m2\begin{align} n\ge m\\ f(n)\ge m^2 \end{align}

We will consider octal to binary encoder circuit for the explanation:

Block diagram

Block diagram of a octal to binary encoder

Truth table

D0D_0D1D_1D2D_2D3D_3D4D_4D5D_5D6D_6D7D_7B1B_1B2B_2B3B_3
10000000000
01000000001
00100000010
00010000011
00001000100
00000100101
00000010110
00000001111

Circuit diagram

Circuit diagram of a octal to binary encoder

Working

  • It has 8 input lines. Only one is active at a time.
  • It has 3 output lines which generates binary code for the octal number that is active.
  • From the above truth table B0B_0 must be 1 whenever the input D1D_1, or D3D_3, or D5D_5, or D7D_7 is high. Thus we can say the following:
    • B0=D1+D3+D5+D7B_0=D_1+D_3+D_5+D_7
    • B1=D2+D3+D6+D7B_1=D_2+D_3+D_6+D_7
    • B2=D4+D5+D6+D7B_2=D_4+D_5+D_6+D_7
  • For example: if D5D_5 is active, OR gates will have 101 as output.
  • Similarly other cases show different outputs, for their respective DnD_n inputs.
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